1. Field of the Invention
The present invention relates to phase locked loop circuits. More particularly, the present invention relates to a phase locked loop employing a fractional frequency synthesizer as a variable oscillator.
2. Description of the Prior Art
Various communication systems may propagate a clock signal, for example, when cascading a series of signal repeaters or when self-servo writing a disk drive. The clock signal may be propagated numerous times using similar or identical timing recovery circuits. In the case of the cascaded signal repeaters, the timing recovery circuits may be physically distinct, such as every few miles. In the case of self-servo writing a disk drive, a single timing recovery circuit is used to repetitively propagate a write clock from a previously written track to a subsequently written track tens of thousands of times. Any imperfection in replicating the clock signal will grow exponentially due to cascading a large number of multiplicative effects.
A conventional timing recovery circuit typically comprises a phase locked loop (PLL) 2 as shown in FIG. 1. The PLL 2 comprises a voltage controlled oscillator (VCO) 4 for outputting a propagated clock signal 6 by frequency/phase locking to an input clock signal 8. A phase detector 10 detects a phase error 12 between the output signal 6 and the input signal 8. A loop filter 14 filters the phase error 12 to generate a control signal 16 applied to the VCO 4. The loop filter 14 determines the type and order of the closed loop system.
A low order PLL (such as a Type 0, or uncompensated type I) will not properly reject static errors in the VCO 4 and therefore are not suitable for propagating a clock signal. A higher order PLL (such as a compensated type I or Type II and higher) will exhibit overshoot (|G| greater than 1) in at least part of the closed-loop frequency response which can cause uncontrolled systematic error growth in propagating a clock signal. Although various techniques have been suggested to address these drawbacks, further improvements are desirable.
The present invention may be regarded as a phase locked loop (PLL) circuit comprising an input for receiving an input oscillating signal, and an output for outputting an output oscillating signal. A first phase detector generates a first phase error between the input oscillating signal and the output oscillating signal. A fractional frequency synthesizer (FFS) generates the output oscillating signal in response to the first phase error, the FFS comprising an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr. The variable I is an integer value, and the variable Fr is a fractional value, both of which are generated in response to the first phase error.
In one embodiment the FFS further comprises a first integer divider for integer dividing a frequency of the reference oscillating signal by an integer X1 to generate an integer divided oscillating signal, and a second integer divider for integer dividing a frequency of the output oscillating signal by at least two integers, including integer X2 selected during a first time interval and an integer X3 selected during a second time interval, to effectively divide the output oscillating signal by the value (I+Fr) to generate a fractionally divided oscillating signal. The FFS further comprises a second phase detector for generating a second phase error between the integer divided oscillating signal and the fractionally divided oscillating signal, and a variable oscillator, responsive to the second phase error, for generating the output oscillating signal.
In one embodiment, the FFS further comprises a loop filter for filtering the second phase error to generate a control signal applied to the variable oscillator.
In one embodiment, X3=X2+1. In an alternative embodiment, the FFS further comprises a dither function modulator responsive to Fr for generating a switching sequence. The switching sequence selects between at least the X2 and X3 integers as the denominator for the second integer divider. In one embodiment, the dither function modulator comprises a sigma-delta dither function.
In another embodiment, the FFS further comprises a compensator for attenuating a periodic error in the second phase error to generate a compensated phase error. In one embodiment, the FFS further comprises a loop filter for filtering the compensated phase error to generate a control signal applied to the variable oscillator.
In yet another embodiment, the PLL circuit further comprises an amplifier for amplifying the first phase error by a gain.
The present invention may also be regarded as a method of frequency locking an output oscillating signal to an input oscillating signal. A first phase error is generated between the input oscillating signal and the output oscillating signal. Variables I and Fr are generated in response to the first phase error, where I is an integer value and Fr is a fractional value. A frequency of a selected oscillating signal is divided by (I+Fr).
The present invention may also be regarded as a self-servo writing disk drive comprising a disk having a plurality of concentric tracks, and a head connected to a distal end of an actuator arm. The head for servo-writing a plurality of the tracks by writing embedded servo sectors at a predetermined interval around the circumference of the disk. The head also for reading a first write clock from a previously servo-written track, the first write clock for writing the embedded servo sectors and a second write clock to a subsequent track. The disk drive further comprises a preamp circuit for generating a write signal applied to the head for writing the embedded servo sectors and the second write clock to the subsequent track, and a phase locked loop (PLL) for generating a clock signal for use in writing the embedded servo sectors and the second write clock to the subsequent track. The PLL comprises an input for receiving an input oscillating signal representing the first write clock, an output for outputting an output oscillating signal used to generate the clock signal, a first phase detector for generating a first phase error between the input oscillating signal and the output oscillating signal, and a fractional frequency synthesizer (FFS) for generating the output oscillating signal in response to the first phase error. The FFS comprises an input for receiving a reference oscillating signal, and a fractional divider responsive to variables I and Fr, wherein I is an integer, Fr is a fractional value, and the variables I and Fr are generated in response to the first phase error.